Design for Testability (DFT) is an important requirement for today's complex application specific integrated circuit (ASIC) designs. DFT techniques allow one to perform high quality manufacturing tests after a chip has been synthesized, and to sort out good chips from bad ones. However, due to the ever increasing complexity of today's designs, the Automatic Test Equipment (ATE) tools required for testing are quite complex and expensive. As a result, manufacturing test costs have become a major part of the overall manufacturing cost of ASICs. Conventional testing approaches are unable to reduce this cost without sacrificing the test quality.
For example, the use of scan based Automatic Test Pattern Generation (ATPG) is a common DFT methodology that is widely used. Scan logic allows internal sequential elements of an ASIC, such as a flip-flops, to be controlled and observed during testing. The flip-flops are connected into several chains, called scan chains, which are usually accessed through test pins. The test pins are normally shared with the functional chip pins. When testing is performed, the test vector data is applied through the chains to control the sequential state of the circuit to a desired state. After application of a test vector, the test response data is captured by the flip-flops. The response data is shifted out through the scan chains and is compared against the expected response to check if the chip is functioning correctly.
In conventional scan chain design, a pair of I/O, or scan-in (SI) and scan-out (SO), pins is used to drive a scan chain, as shown in FIG. 1, which shows an example of shifting scan data through a regular scan chain using a conventional scan chain. Data through the chains shifts with each rising (or falling) edge of the clock. In each clock cycle, scan-in data is applied at the SI pin, and scan-out data is observed at the SO pin. The clock is strobed or pulsed to shift the data through the chain. This process is repeated based on the length of the chain, to completely flush the data out of the chain while filling the chain with new data at the same time.
The number of scan chains is usually limited to 16 or 32. The limit on the number of scan chains is bounded by the number of available input and output (I/O) pins that are able to access the chains, and by the number of scan-channels on the ATE used to drive the chains. For example, if one input and one output pin is required to access each chain, the number of the chains is limited to one half of the number of I/O pins.
The chains are usually balanced as much as possible to minimize the length of the longest chain. The number of tester cycles required to shift data through a chain is determined by the length of the chain, i.e. by the number of flip-flops in the chain. Therefore, the reduction in testing time is limited by the length of the chains.
Due to the large number of scan flip-flops and the long scan chain lengths, the majority of test application time is spent in shifting test data through scan chains. Increasing the number of scan chains would reduce the maximum length of the scan chains, thus reducing the number of test cycles required to shift data through the chains. This directly impacts the test cost by reducing the test application time.
The conventional approaches fail to efficiently and cost-effectively perform tests, because the constraints based on the number of available test pins for accessing chains, and/or the number of available scan channels on a tester usually limit the number of scan chains to 16 or 32. Therefore, the conventional approaches are inadequate for testing integrated circuits, because the required amount of testing time is inefficient for testing modern circuit designs. With the rising cost of performing manufacturing tests, it is critical to reduce the test application time, thereby reducing the test cost.